PCIe spec defined 3 types of AtomicOps transactions:
"AtomicOps are architected for device-to-host, device-to-device, and host-to-device transactions."
If Intel® Xeon® Processor Scalable Family support Pcie AtomicOps host-to-device transactions? The background for this question is it looks in previous Xeon generation, only PCIe AtomicOps device-to-host transactions are supported: "The Intel Xeon processor E7 V2 family supports PCIe atomic operations (as a completer)". Not sure if Scalable family extend the support to host-to-device using X86 ISA based instructions?